1. Field of the Invention
The present invention relates to a polishing apparatus and a polishing method for flattening an uneven surface accompanying for example a multilayer interconnection structure of a semiconductor device and a method for producing a semiconductor device having a multilayer interconnection structure.
2. Description of the Related Art
Along with the increase in integration and reduction of size of semiconductor devices, progress has been made in miniaturization of interconnections, reduction of interconnection pitch, and superposition of interconnections. The importance of the multilayer interconnection technology in the manufacturing process of semiconductor devices is therefore rising.
On the other hand, conventionally aluminum (Al) has been frequently used as an interconnection material of a semiconductor device having a multilayer interconnection structure, but in order to suppress the propagation delay of signals in the recent 0.25 xcexcm design rule, there is active development of an interconnection process replacing the aluminum (Al) of the interconnection material by copper (Cu). When using Cu for interconnections, there is the merit that both a low resistance and a high electromigration tolerance can be obtained.
In a process using this Cu for interconnections, for example, an interconnection process referred to as the damascene process for burying a metal in a groove-like interconnection pattern formed in an interlayer insulation film in advance, removing excess metal film by a chemical mechanical polishing (CMP) process, and thereby forming the interconnections has become influential. The damascene process has the characteristics that etching of the interconnections becomes unnecessary and also a further upper interlayer insulation film becomes flat by itself, so the manufacturing steps can be simplified.
Further, in the dual damascene process, where not only the interconnections, but also the contact holes are formed as grooves in the interlayer insulation film and the interconnections and the contact holes are simultaneously buried by the metal, further great reduction of the interconnection process becomes possible.
Here, an explanation will be made of an example of the process for forming interconnections by the dual damascene process by referring to FIG. 32 to FIG. 37. Note that the explanation will be made of the case where Cu is used as the interconnection material.
First, as shown in FIG. 32, for example, an interlayer insulation film 302 made of for example a silicon oxide film is formed for example, by a low pressure chemical vapor deposition (CVD) process on a substrate 301 made of silicon or another semiconductor on which a not illustrated impurity diffusion layer is appropriately formed.
Next, as shown in FIG. 33, contact holes 303 communicating with the impurity diffusion region of the substrate 301 and grooves 304 in which a predetermined pattern of interconnections to be electrically connected to the impurity diffusion region of the substrate 301 is to be formed are formed by using a well known photolithography technique and etching technique.
Next, as shown in FIG. 34, a barrier film 305 is formed on the surface of the interlayer insulation film 302 and in the contact holes 303 and the grooves 304. This barrier film 305 is formed by a material such as for example Ta, Ti, TaN, or TiN by the well known sputtering process. The barrier film 305 is provided so as to prevent diffusion of the material comprising the interconnections into the inter-layer insulation film 302. Particularly, in a case where the interconnection material is Cu and the inter-layer insulation film 302 is a silicon oxide film, Cu has a large diffusion coefficient with respect to the silicon oxide film and is easily oxidized, so this is prevented.
Next, as shown in FIG. 35, a seed Cu film 306 is formed on the barrier film 305 to a predetermined thickness by a well known sputtering process, then, as shown in FIG. 36, a Cu film 307 is formed so as to bury the contact holes 303 and the grooves 304 by Cu. The Cu film 307 is formed by for example a plating process, CVD process, sputtering process, etc.
Next, as shown in FIG. 37, an excess Cu film 307 and barrier film 305 on the inter-layer insulation film 302 are removed by the CMP process and flattened.
Due to this, interconnections 308 and contacts 309 are formed.
By repeating the above process on the interconnections 308, the multilayer interconnections can be formed.
Summarizing the problems to be solved by the invention, in the step of removing the excess Cu film 307 and barrier film 305 by the CMP process in the multilayer interconnection forming process using the dual damascene process, the removal performance differs between the inter-layer insulation film 302 and the Cu film 307 and barrier film 305, therefore there has been the disadvantage that dishing, erosion (thinning), recesses, etc. easily occur in the interconnections 308.
Dishing is a phenomenon where, as shown in FIG. 38, when there is an interconnection 308 having a wide width of for example about 100 xcexcm at a design rule of for example the 0.18 xcexcm rule, the center portion of the interconnection is excessively removed and sinks: If this dishing occurs, the sectional area of the interconnection 308 becomes insufficient. This becomes a cause of poor interconnection resistance etc. This dishing is apt to occur when copper or aluminum, which is relatively soft, is used as the interconnection material.
Erosion is a phenomenon where, as shown in FIG. 39, a portion having a high pattern density where interconnections with a width of 1.0 xcexcm are formed at a density of 50% in a range of for example 3000 xcexcm are excessively removed. When erosion occurs, the sectional area of the interconnections becomes insufficient. This becomes a cause of poor interconnection resistance etc.
Recess, or xe2x80x9crecessingxe2x80x9d is a phenomenon where, as shown in FIG. 40, the interconnection 308 becomes low at the interface between the inter-layer insulation film 302 and the interconnection 308. In this case as well, the sectional area of the interconnections becomes insufficient. This becomes a cause of poor interconnection resistance etc.
Further, in the step of removing the excess Cu film 307 and barrier film 305 by the CMP process, it is necessary to efficiently remove the Cu film 307 and barrier film 305. The amount of removal per unit time, that is, the polishing rate, is required to become for example more than 500 nm/min. In order to obtain this polishing rate, it is necessary to increase the polishing pressure with respect to the wafer. When the polishing pressure is raised, as shown in FIG. 41, a scratch SC and chemical damage CD are apt to occur in the interconnection surface. In particular, they easily occur in the soft Cu or aluminum. For this reason, it becomes a cause of opening of the interconnections, short-circuiting, poor interconnection resistance, and other disadvantages. Further, if the polishing pressure is raised, there is the inconvenience that the amount of the occurrence of dishing, erosion, and recesses becomes larger.
An object of the present invention is to provide a polishing apparatus and a polishing method and a method for producing a semiconductor device capable of easily flattening an initial unevenness when flattening a metal film such as an interconnection of a semiconductor device having a multilayer interconnection structure by polishing and excellent in efficiency of removal of the excess metal film and capable of suppressing occurrence of excessive removal of the metal film such as dishing and erosion.
To attain the above object, a polishing apparatus of the present invention is provided with a polishing tool having a polishing surface and having conductivity, a polishing tool rotating and holding means for rotating the polishing tool about a predetermined axis of rotation and holding the same, a rotating and holding means for holding a polishing object and rotating the same about a predetermined axis of rotation, a movement and positioning means for moving and positioning the polishing tool to a target position in a direction facing the polishing object, a relative moving means for making the polished surface of the polishing object and the polishing surface of the polishing tool relatively move along a predetermined plane, an electrolyte feeding means for feeding an electrolyte onto the polished surface of the polishing object, and an electrolytic current supplying means for supplying an electrolytic current flowing through the polishing tool through the electrolyte from the polished surface by using the polished surface of the polishing object as an anode and the polishing tool as a cathode.
Further, the polishing apparatus of the present invention is a polishing apparatus which is provided with a polishing tool having a polishing surface which contacts the entire surface of the polished surface of the polishing object while rotating and which brings the polishing object into contact with the polished surface while rotating it so as to flatten and polish the same, wherein the apparatus further has an electrolyte feeding means for feeding an electrolyte onto the polishing surface, is provided with an anode electrode and a cathode electrode capable of supplying electric power to the polished surface of the polishing object in the polishing surface, and flattens and polishes the polished surface of the polishing object by electrolytic composite polishing which combines electrolytic polishing by the electrolyte and mechanical polishing by the polishing surface.
The polishing method of the present invention comprises pushing the polishing surface of a conductive polishing tool and the surface of the polishing object with a metal film formed on at least the surface or an inner layer against each other while interposing the electrolyte therebetween, supplying the electrolytic current flowing from the surface of the polishing object to the polishing tool through the electrolyte by using the polishing tool as a cathode and the surface of the polishing object as an anode, making the polishing tool and the polishing object move relatively along a predetermined plane while rotating the two, and flattening the metal film formed on the polishing object by electrolytic composite polishing combining electrolytic polishing by the electrolyte and mechanical polishing by the polishing surface.
Further, a polishing method of the present invention comprises a step of forming a passivation film exhibiting a function of preventing an electrolytic reaction of the metal film at the surface of the metal film formed on the polishing object; a step of pushing the polishing surface of a conductive polishing tool and a metal film against each together while interposing an electrolyte between the polishing surface and the metal film, and then applying a predetermined voltage between the polishing tool and the metal film; a step of making the polishing surface of the polishing tool and the metal film of the polishing object move relatively along a predetermined plane and selectively removing a passivation film on a projecting portion projected from the polishing surface of the polishing tool in the metal film by mechanical polishing by the polishing tool; and a step of removing a projecting portion of the metal film exposed at the surface due to the removal of the passivation film by the electrolytic polishing function by the electrolyte and flattening the metal film.
A method for producing a semiconductor device of the present invention comprises a step of forming an interconnection use groove for forming an interconnection in an insulation film formed on a substrate, a step of stacking a metal film on the insulation film so as to bury the interconnection use groove, a step of forming a passivation film exhibiting a function of preventing the electrolytic reaction of the metal film at the surface of the metal film stacked on the insulation film, a step of selectively removing the passivation film on a projecting portion existing at the surface of the metal film generated by the burying of the interconnection use groove in the passivation film formed on the metal film by mechanical polishing and thereby exposing the projecting portion of the related metal at the surface, and a step of removing the projecting portion of the exposed metal film by electrolytic polishing and flattening the unevenness of the surface of the metal film generated due to the burying of the interconnection use groove.
Further, the method for producing the semiconductor device of the present invention further comprises a step of removing the excess metal film existing on the insulation film of the metal film with the surface flattened by electrolytic composite polishing combining electrolytic polishing and mechanical polishing to thereby form the interconnection.
In the method of production of the semiconductor device of the present invention, by forming a passivation film on a metal film having unevenness at its surface and mechanically removing the passivation film, a projecting portion of the metal film is exposed at the surface. The projecting portion of this metal film is selectively eluted by the electrolytic action of the electrolyte using the remaining passivation film as a mask. As a result, the initial unevenness of the metal film is flattened.
Further, the metal film with the initial unevenness flattened is highly efficiently removed by the electrolytic composite polishing. For example, the excess metal film existing on the insulation film is highly efficiently removed when forming the interconnection.
When the excess metal film is removed and the insulation film is exposed, the electrolytic action at that portion automatically stops, so the metal film buried in the interconnection use groove formed in the insulation film is not excessively removed.